Switching Activity Analysis and Optimization Methods for Promoting FunctionallyAppropriate Test and Delay Characterization in Digital Integrated Circuits

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Overview

Title
Switching Activity Analysis and Optimization Methods for Promoting FunctionallyAppropriate Test and Delay Characterization in Digital Integrated Circuits
Contributors
Alpaslan, Meryem E (creator)
Dworak, Jennifer (Director)
Bahar, Iris (Reader)
Tadesse, Desta (Reader)
Brown University. ENGINEERING: Electrical Science and Computer Engineering (sponsor)
Doi
10.7301/Z0FN14FH
Copyright Date
2011
Abstract
This dissertation utilizes Design for testability, DFT-, and automatic test patterngeneration, ATPG-based, techniques to overcome various problems that are caused bythe non-functional switching activity of the circuit during scan-based test. Switchingactivity discrepancies between a circuit�s functional and test modes are problematic for avariety of reasons. When switching activity is excessive, it may damage chips or causeworking parts to be considered defective�leading to yield loss. In other cases, very lowswitching activity during test may lead to test escapes. In this dissertation, thecharacteristics and the nature of the hazardous switching activity have been studiedduring circuit�s test and functional mode. A quantitative comparison of the amount andthe profile of the switching activity for different modes of operation has been performed.Motivated by the outcomes of our activity analysis for scan shift, we developed aDFT-based technique which relies on inserting extra test points to a subset of the flipflopsin the verified circuit such that the transitions at the outputs of these selected flipflopswill be blocked from propagating to the combinational parts of the design. Theproposed technique modifies the circuit at register-transfer level, RTL, such that thetiming violations due to the inserted extra hardware will be handled by the synthesis tool.With the proposed method, the excessive switching activity during the shift cycles of thescan test will be reduced with an insignificant area overhead.We also developed a noise index model, NIM, which can be effectively used tocapture the effects of the excessive switching activity around a critical path during thelaunch clock cycle on the delay of the path. We have validated the effectiveness of ournoise index model on an industrial size circuit to estimate the delay discrepanciesbetween the silicon measurements and pre-silicon simulation estimations.We then used our noise index model for high-quality path delay patterngeneration by utilizing the large fraction of the don�t care bits in the test cubes. Throughour noise index model based X�filling method, we replicated the worst observedfunctional switching activity profile around the critical path of interest. We used thismodel to overcome the over-testing and under-testing problems of the path delay test.
Keywords
Design For Testability
Automatic Test Pattern Generation
Switching Activity
Delay Test
Notes
Thesis (Ph.D. -- Brown University (2011)
Extent
iii, 126 p.

Citation

Alpaslan, Meryem E., "Switching Activity Analysis and Optimization Methods for Promoting FunctionallyAppropriate Test and Delay Characterization in Digital Integrated Circuits" (2011). Electrical Sciences and Computer Engineering Theses and Dissertations. Brown Digital Repository. Brown University Library. https://doi.org/10.7301/Z0FN14FH

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