- Title Information
- Title
- Concurrent Algorithms for Emerging Hardware Platforms
- Name:
Personal
- Name Part
- Calciu, Irina
- Role
- Role Term:
Text
- creator
- Origin Information
- Copyright Date
- 2015
- Physical Description
- Extent
- xi, 126 p.
- digitalOrigin
- born digital
- Note
- Thesis (Ph.D. -- Brown University (2015)
- Name:
Personal
- Name Part
- Herlihy, Maurice
- Role
- Role Term:
Text
- Director
- Name:
Personal
- Name Part
- Gottschlich, Justin
- Role
- Role Term:
Text
- Director
- Name:
Personal
- Name Part
- Fonseca, Rodrigo
- Role
- Role Term:
Text
- Reader
- Name:
Corporate
- Name Part
- Brown University. Computer Science
- Role
- Role Term:
Text
- sponsor
- Genre (aat)
- theses
- Abstract
- Computer architecture has recently seen an explosion of innovation that has enabled more parallel execution, while parallel software systems have been making strides in providing more simplified programming models. The number of computing cores used in every area of the software ecosystem continues to increase, and parallelism within programs is now ubiquitous. Ideally, performance would scale linearly with the number of cores, but that is rarely the case in practice. Communication and synchronization between cores running the same application are often necessary, but usually come at a high cost. This results in reduced scalability and a significant drop in performance. In this context, parallel software needs to provide more simplified programming patterns and tools that enable a higher potential for parallelism without increasing the burden on the programmer.
This thesis discusses new techniques to simplify writing efficient parallel code by leveraging novel architectural features from many current systems. First, we describe various programming abstractions, such as delegation, elimination, combining and transactional memory, which improve scalability and performance of concurrent programs. Next, we show how to use and integrate these abstractions to write scalable concurrent algorithms, such as stacks and priority queues. Finally, we describe how to further improve these abstractions. In particular, we present new transactional memory algorithms that use Intel’s new extension to the x86 instruction set architecture, called Restricted Transactional Memory, to simplify general synchronization. Developers can use all of these abstractions as building blocks to create efficient code that is able to scale on very diverse platforms, with minimal specialized knowledge of parallel programming.
- Subject
- Topic
- concurrent algorithms
- Subject
- Topic
- concurrent data structures
- Subject
- Topic
- NUMA-aware data structures
- Subject
- Topic
- transactional memory
- Record Information
- Record Content Source (marcorg)
- RPB
- Record Creation Date
(encoding="iso8601")
- 20150601
- Language
- Language Term:
Code (ISO639-2B)
- eng
- Language Term:
Text
- English
- Identifier:
DOI
- 10.7301/Z0NK3CDW
- Access Condition:
rights statement
(href="http://rightsstatements.org/vocab/InC/1.0/")
- In Copyright
- Access Condition:
restriction on access
- Collection is open for research.
- Type of Resource (primo)
- dissertations