Approximate Computing Techniques For Accuracy-Energy Trade-offs
Hashemi, Soheil (creator)
Reda, Sherief (Advisor)
Silverman, Harvey (Reader)
Taubin, Gabriel (Reader)
Fonseca, Rodrigo (Reader)
Brown University. Engineering: Electrical Sciences and Computer Engineering (sponsor)
Power efficiency has emerged as one of the main concerns in many digital design domains ranging from embedded and battery operated systems to data centers. As a result, in recent years, many different approaches have been aimed at lowering the power and resource footprints of computing systems. Approximate computing is one such emerging technique targeting error resilient applications and offering promising benefits. Approximate computing introduces design accuracy as a third orthogonal dimension to the conventional power/performance trade-offs. The underlying principal of such approach is that with relaxing the full accuracy requirement on the output, one can benefit from significant savings in hardware design metrics, such as power consumption, design area, and critical path delay.
This paradigm, however, is only applicable to applications where an inherent tolerance to small and insignificant errors exists. Applications in domains of media processing, machine learning, and data mining are a few examples. Interestingly, with the recent growth in the number of data intensive and machine learning applications, the relevance of approximate computing has only increased.
This thesis makes the following contributions toward the advance of approximate computing techniques in different computing systems. First, we propose and evaluate a novel methodology for design of approximate arithmetic blocks, namely multipliers and dividers. Our methodology benefits from a dynamic truncation scheme, where the most important bits are guaranteed to be selected, as well as an unbiasing scheme, where the error distribution in balanced around zero to ensure both positive and negative errors. We show that our methodology can achieve up to 71.45% in power savings for an average error of 1.47%, and up to 70.81% in power savings for and average error of 3.08%, for the approximate multiplier and the approximate divider, respectively.
Second, using Boolean matrix factorization (BMF), we devise an approximate synthesis methodology, where any circuit can be reduced to an approximate variant in an automated fashion. We devise a BMF algorithm to give more weight to approximations on higher bit indices compared to their least significant counterparts. We evaluate our proposed methodology on six different circuits and show benefits of up to 47.55% in power reduction for a tight error bound of 5%.
Next, and to showcase the applicability of approximate computing techniques to complex computing pipelines, we explore such techniques for case studies from two different application domains.
Here, we first explore the energy-accuracy trade-offs while using different bit precisions and quantization techniques for deep learning applications. We devise training time techniques to minimize the accuracy degradation as a result of lower precisions. We also propose the utilization of augmented network topologies to claim back the accuracy degradation while still offering significant hardware benefits. As one data point, and for CIFAR-10 dataset, we report energy savings of up to 36% for an augmented network based on powers-of-two weight, and while maintaining classification accuracy.
Finally, we evaluate the accuracy-performance frontiers of a biometric security system (more specifically an iris recognition system) by identifying approximation knobs throughout the processing pipeline and exploring the resulting design space. We deploy an end-to-end system, where images are captured using an infrared camera and processed through a HW/SW co-designed pipeline implemented on an FPGA board. Our introduced approximations result in 48x speedup in runtime compared on an already hardware accelerated design while maintaining industry standard levels of accuracy.